Invention Grant
- Patent Title: Memory device with serial and parallel testing structure for sensing amplifiers
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Application No.: US17844557Application Date: 2022-06-20
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Publication No.: US12254938B2Publication Date: 2025-03-18
- Inventor: ALberto Troia , Antonino Mondello
- Applicant: Lodestar Licensing Group LLC
- Applicant Address: US IL Evanston
- Assignee: Lodestar Licensing Group LLC
- Current Assignee: Lodestar Licensing Group LLC
- Current Assignee Address: US IL Evanston
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G11C29/32
- IPC: G11C29/32 ; G11C29/02 ; G11C29/06 ; G11C29/12 ; G11C29/42

Abstract:
An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.
Public/Granted literature
- US20230410930A1 MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE Public/Granted day:2023-12-21
Information query
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