Invention Grant
- Patent Title: Layouts of data pads on a semiconductor die
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Application No.: US17646565Application Date: 2021-12-30
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Publication No.: US12255198B2Publication Date: 2025-03-18
- Inventor: Takamasa Suzuki
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L27/02
- IPC: H01L27/02 ; G11C5/06 ; H01L25/065

Abstract:
Layouts of data pads and dummy data pads are disclosed. A die may include a number of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge. The die may further include a first number of data pads variously electrically coupled to the number of circuits and arranged proximate to the first edge and a first number of dummy data pads, not electrically coupled to the number of circuits, alternatingly arranged with the first number of data pads, and proximate to the first edge. The die may further include a second number of data pads arranged proximate to the third edge and a second number of dummy data pads, alternatingly arranged with the second number of data pads, and proximate to the third edge. Associated devices, systems, and methods are also disclosed.
Public/Granted literature
- US20230215858A1 LAYOUTS OF DATA PADS ON A SEMICONDUCTOR DIE Public/Granted day:2023-07-06
Information query
IPC分类: