Invention Grant
- Patent Title: Accelerated read translation path in memory sub-system
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Application No.: US17703759Application Date: 2022-03-24
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Publication No.: US12265725B2Publication Date: 2025-04-01
- Inventor: Johnny A. Lam
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/02 ; G06F12/1009

Abstract:
A system includes a non-volatile memory device and a processing device to perform operations including creating a logical transfer unit (LTU) corresponding to a logical block address (LBA) received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of LBA space of the non-volatile memory device, wherein one of the subset is the LBA. The processing device comprises a hardware accelerator to perform operations comprising: retrieving, using an LTU identifier associated with the LTU, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space; and providing the metadata for use in determining and utilizing the physical address to perform a read operation specified by the read request.
Public/Granted literature
- US20220214830A1 ACCELERATED READ TRANSLATION PATH IN MEMORY SUB-SYSTEM Public/Granted day:2022-07-07
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