Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.