- Patent Title: Integrated circuitry, a memory array comprising strings of memory cells, a method used in forming a conductive via, a method used in forming a memory array comprising strings of memory cells
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Application No.: US18416243Application Date: 2024-01-18
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Publication No.: US12266569B2Publication Date: 2025-04-01
- Inventor: John D. Hopkins , Shuangqiang Luo , Alyssa N. Scarbrough
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L21/768 ; H10B41/27 ; H10B43/27
Abstract:
Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.
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