Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

Invention Grant

US12266575B2 Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same 有权

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Patent Title: Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same
Application No.: US18432251

Application Date: 2024-02-05
Publication No.: US12266575B2

Publication Date: 2025-04-01
Inventor: Chih-Wei Lee , Wen-Hung Huang , Kuo-Feng Yu , Jian-Hao Chen , Hsueh-Ju Chen , Zoe Chen
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: HAYNES AND BOONE, LLP
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/311 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/423 ; H01L29/786

Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

Abstract:

A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Public/Granted literature

US20240243016A1 MULTIPLE GATE FIELD-EFFECT TRANSISTORS HAVING VARIOUS GATE OXIDE THICKNESSES AND METHODS OF FORMING THE SAME Public/Granted day:2024-07-18

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS