Invention Grant
- Patent Title: Transistor with dielectric spacers and method of fabrication therefor
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Application No.: US17661827Application Date: 2022-05-03
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Publication No.: US12266713B2Publication Date: 2025-04-01
- Inventor: Darrell Glenn Hill
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L21/02 ; H01L29/40 ; H01L29/423 ; H01L29/66

Abstract:
A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.
Public/Granted literature
- US20230361198A1 TRANSISTOR WITH DIELECTRIC SPACERS AND METHOD OF FABRICATION THEREFOR Public/Granted day:2023-11-09
Information query
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