A memory device includes a gate stack structure, a channel pillar, a plurality of conductive pillars, and a charge storage structure. The gate stack structure is located over a dielectric substrate, and includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel pillar extends through the gate stack structure. Each of the conductive pillars includes a body portion and an extension portion. The body portion extends through the gate stack structure and is electrically connected to the channel pillar. The extension portion is below and is electrically isolated from the channel pillar. The charge storage structure is between the channel pillar and the plurality of gate layers.