Invention Grant
- Patent Title: Method and related apparatus for improving memory cell performance in semiconductor-on-insulator technology
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Application No.: US17734315Application Date: 2022-05-02
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Publication No.: US12274074B2Publication Date: 2025-04-08
- Inventor: Jack Liu , Charles Chew-Yuen Young
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; H10B61/00 ; H10N50/80 ; G11C13/00

Abstract:
In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.
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