Invention Grant
- Patent Title: Method for manfacturing semiconductor device for reducing partcle-induced defects
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Application No.: US17741589Application Date: 2022-05-11
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Publication No.: US12278142B2Publication Date: 2025-04-15
- Inventor: Li-Han Lin , Jr-Chiuan Wang
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
A method for manufacturing a semiconductor structure including the following steps is provided. First, a first insulating layer with a conductive contact is formed over a substrate, and a second insulating layer having an opening is formed on the first insulating layer, wherein the opening corresponds to and exposes a top surface of the conductive contact. A conductive line structure is formed in the opening, wherein a contact void is formed between the second insulating layer and the conductive line structure, and then a plasma oxide layer is conformally deposited over the substrate. Then, a wet cleaning process is performed by using an aqueous solution containing negatively charged ions. A capping layer is formed on the plasma oxide layer, the capping layer filling the contact void, and an etching back process to remove the capping layer above the contact void.
Public/Granted literature
- US20230369104A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2023-11-16
Information query
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