Invention Grant
- Patent Title: Substrate frame design for three-dimensional stacked electronic assemblies and method for the same
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Application No.: US17851754Application Date: 2022-06-28
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Publication No.: US12278172B2Publication Date: 2025-04-15
- Inventor: Akash Agrawal , Prashanth Ganeshbaabu
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/498
- IPC: H01L23/498 ; G06F30/398 ; H05K1/18 ; H05K3/30 ; G06F115/12 ; H01L25/00 ; H01L25/10

Abstract:
In order to relieve the stress on the substrates in a 3D stacked electronic assembly, a substrate frame is divided into a plurality of frame sections that are separated by spaces between the frame sections. These separations allow the substrates to expand/contract in response to temperature variations and other environmental conditions, and generally allow the substrates to move in one or more axial directions. The separations between the substrate portions are design-specific for each substrate design. The placement of IC packages on either side of the substrate is analyzed to identify areas of maximal warpage through physical measurements, physical model simulations, or using a trained neural network. The spaces in the substrate frame are then be placed next to or aligned with the areas of maximal warpage to reduce the stress on the substrate.
Public/Granted literature
- US20230420351A1 SUBSTRATE FRAME DESIGN FOR THREE-DIMENSIONAL STACKED ELECTRONIC ASSEMBLIES Public/Granted day:2023-12-28
Information query
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