Invention Grant
- Patent Title: Bias techniques for amplifiers with mixed polarity transistor stacks
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Application No.: US18316896Application Date: 2023-05-12
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Publication No.: US12278597B2Publication Date: 2025-04-15
- Inventor: John Birkbeck
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Steinfl + Bruno LLP
- Main IPC: H03F1/22
- IPC: H03F1/22 ; H03F3/193 ; H03F3/45

Abstract:
Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.
Public/Granted literature
- US20230353099A1 BIAS TECHNIQUES FOR AMPLIFIERS WITH MIXED POLARITY TRANSISTOR STACKS Public/Granted day:2023-11-02
Information query
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