Invention Grant
- Patent Title: Laminate, laminate with buildup layer, laminate with metal foil, and circuit board
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Application No.: US18266627Application Date: 2020-12-17
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Publication No.: US12284755B2Publication Date: 2025-04-22
- Inventor: Koichiro Okamoto
- Applicant: SEKISUI KASEI CO., LTD.
- Applicant Address: JP Osaka
- Assignee: SEKISUI KASEI CO., LTD.
- Current Assignee: SEKISUI KASEI CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: GREENBLUM & BERNSTEIN, P.L.C.
- International Application: PCT/JP2020/047204 WO 20201217
- International Announcement: WO2022/130572 WO 20220623
- Main IPC: H05K1/03
- IPC: H05K1/03 ; H05K3/46

Abstract:
There are provided a laminate and the like and a circuit board including the same that exhibit an excellent low dielectric property by a non-conventional new approach. The laminate according to an embodiment of the present invention is a laminate used for a core layer of a circuit board, in which the laminate does not include a buildup layer, the laminate is obtained by laminating a plurality of prepregs including a fiber base material layer and a resin layer (A) so that the prepregs are in direct contact with each other, the resin layer (A) contains an inorganic filler and hollow resin particles, and the hollow resin particles are contained in the resin layer (A) in an amount of 1% by weight to 50% by weight with respect to the total amount of the resin layer (A).
Public/Granted literature
- US20240057252A1 LAMINATE, LAMINATE WITH BUILDUP LAYER, LAMINATE WITH METAL FOIL, AND CIRCUIT BOARD Public/Granted day:2024-02-15
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