Invention Grant
- Patent Title: Dual depth junction structures and process methods
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Application No.: US17700858Application Date: 2022-03-22
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Publication No.: US12284839B2Publication Date: 2025-04-22
- Inventor: Hui Zang , Gang Chen
- Applicant: OMNIVISION TECHNOLOGIES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: OMNIVISION TECHNOLOGIES, INC.
- Current Assignee: OMNIVISION TECHNOLOGIES, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Christensen O'Connor Johnson Kindness PLLC
- Main IPC: H01L31/062
- IPC: H01L31/062 ; H01L31/113 ; H10F39/00 ; H10F39/18

Abstract:
Transistors, electronic devices, and methods are provided. Transistors include a gate trench formed in a semiconductor substrate and extending to a gate trench depth, and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductive type. The source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, and the source and the drain each includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends to a depth in the semiconductor substrate deeper than the first doped region relative to a surface of the semiconductor substrate.
Public/Granted literature
- US20230307474A1 DUAL DEPTH JUNCTION STRUCTURES AND PROCESS METHODS Public/Granted day:2023-09-28
Information query
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