Invention Grant
- Patent Title: Multi-dimensional metal first device layout and circuit design
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Application No.: US17740691Application Date: 2022-05-10
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Publication No.: US12288747B2Publication Date: 2025-04-29
- Inventor: H. Jim Fulford , Mark I. Gardner , Partha Mukhopadhyay
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/3105 ; H01L21/762

Abstract:
Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.
Public/Granted literature
- US20230057139A1 MULTI-DIMENSIONAL METAL FIRST DEVICE LAYOUT AND CIRCUIT DESIGN Public/Granted day:2023-02-23
Information query
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