Invention Grant
- Patent Title: Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts
-
Application No.: US18524942Application Date: 2023-11-30
-
Publication No.: US12293187B2Publication Date: 2025-05-06
- Inventor: Douglas Vanesko , Tony M. Brewer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/32 ; G06F9/38

Abstract:
Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
Public/Granted literature
Information query