Invention Grant
- Patent Title: Semiconductor device with self-aligned vias
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Application No.: US17750887Application Date: 2022-05-23
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Publication No.: US12293944B2Publication Date: 2025-05-06
- Inventor: Chien-Han Chen , Chien-Chih Chiu , Ming-Chung Liang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/02 ; H01L23/522 ; H01L21/311 ; H01L21/3213 ; H01L23/532

Abstract:
A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.
Public/Granted literature
- US20220285216A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED VIAS Public/Granted day:2022-09-08
Information query
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