Invention Grant
- Patent Title: Method of manufacturing semiconductor element and semiconductor element
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Application No.: US18407011Application Date: 2024-01-08
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Publication No.: US12300547B2Publication Date: 2025-05-13
- Inventor: Kazuki Yamaguchi , Yoshitaka Sumitomo
- Applicant: NICHIA CORPORATION
- Applicant Address: JP Anan
- Assignee: NICHIA CORPORATION
- Current Assignee: NICHIA CORPORATION
- Current Assignee Address: JP Anan
- Agency: Foley & Lardner LLP
- Priority: JP2020-090108 20200522,JP2021-075885 20210428
- Main IPC: H01L21/78
- IPC: H01L21/78 ; B23K26/40 ; B23K26/53 ; H01L23/544 ; B23K101/40

Abstract:
A semiconductor element includes: a substrate having a first surface, a second surface, and at least one lateral surface; and a semiconductor layer formed on the second surface. The at least one lateral surface includes: at least one flat region, a first region that extends along a first direction parallel to the first surface at a position apart from the first surface and the second surface, wherein a surface roughness of the first region is larger than a surface roughness of the flat region, and a second region that extends along the first direction parallel to the first surface at a position between the first region and the first surface and apart from the first surface, wherein a surface roughness of the second region is larger than the surface roughness of the flat region. The substrate includes, in an interior of the substrate, a plurality of modified portions.
Public/Granted literature
- US20240178066A1 METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT Public/Granted day:2024-05-30
Information query
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