Invention Grant
- Patent Title: And manufacture of robust, high-performance devices
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Application No.: US17231301Application Date: 2021-04-15
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Publication No.: US12302612B2Publication Date: 2025-05-13
- Inventor: Siddarth Sundaresan , Ranbir Singh , Jaehoon Park
- Applicant: GeneSiC Semiconductor Inc.
- Applicant Address: US VA Dulles
- Assignee: GeneSiC Semiconductor Inc.
- Current Assignee: GeneSiC Semiconductor Inc.
- Current Assignee Address: US VA Dulles
- Agency: Davé Law Group, LLC
- Agent Raj S. Davé
- Main IPC: H10D62/10
- IPC: H10D62/10 ; H01L21/04 ; H10D12/01 ; H10D30/66 ; H10D62/17 ; H10D62/832

Abstract:
An embodiment relates to a device comprising SiC, the device having a p-shield region that is outside a junction gate field-effect transistor region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform. Another embodiment relates to a device comprising SiC, the device having a p-shield region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform, wherein at least a portion of the p-shield region is located within the p-well region.
Public/Granted literature
- US20210257447A1 DESIGN AND MANUFACTURE OF ROBUST, HIGH-PERFORMANCE DEVICES Public/Granted day:2021-08-19
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