Semiconductor package
Abstract:
Disclosed is a semiconductor package comprising a semiconductor chip, a redistribution pattern on a bottom surface of the semiconductor chip and coupled to the semiconductor chip, a protection layer that covers a bottom surface of the redistribution pattern, a conductive pattern on a bottom surface of the protection layer and coupled to the redistribution pattern, a buffer pattern in contact with a bottom surface of a first part of the conductive pattern and with the bottom surface of the protection layer, and an under bump pattern on a bottom surface of the second part of the conductive pattern and covering a bottom surface and a side surface of the buffer pattern. The under bump pattern is coupled to the second part of the conductive pattern.
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