Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US18593536Application Date: 2024-03-01
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Publication No.: US12315854B2Publication Date: 2025-05-27
- Inventor: Chen-Hua Yu , Wei Ling Chang , Chuei-Tang Wang , Chieh-Yen Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/00

Abstract:
In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
Public/Granted literature
- US20240258286A1 INTEGRATED CIRCUIT PACKAGE AND METHOD Public/Granted day:2024-08-01
Information query
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