Invention Grant
- Patent Title: Method for forming a first and a second transistors array having plurality of first and semiconductor pillars
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Application No.: US17879779Application Date: 2022-08-03
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Publication No.: US12317484B2Publication Date: 2025-05-27
- Inventor: Guangsu Shao , Deyuan Xiao
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN202210681886.5 20220615
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array including a plurality of first semiconductor pillars; forming first word lines, each of the plurality of first semiconductor pillars being connected to a corresponding one of the first word lines and a corresponding one of the plurality of first bit lines; forming a second transistor array on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, and the plurality of first semiconductor pillars being corresponding to the plurality of second semiconductor pillars one to one; and forming second word lines and second bit lines to form a 2T0C semiconductor structure.
Public/Granted literature
- US20230413537A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF Public/Granted day:2023-12-21
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