A preprocessing module receives a word line activation command and a clock signal and outputs a word line address corresponding to a current word line activation command as a word line address signal when a count value reaches a preset value. An address processing module counts all received word line address signals and outputs a word line address signal with the largest number of occurrences as a row hammer address. A first processing unit generates first and second supplementary refresh address according to the row hammer address. A second processing unit generates a normal refresh address according to a refresh command. A refresh unit performs a refresh operation according to an acquired address signal. A control unit selects to output a refresh address or control the refresh unit to select to receive a refresh address.