A system and method for clock distribution in a digital circuit. In some embodiments, the method, includes: modifying a synchronous digital logic circuit, the modifying including: replacing a first D flipflop in the circuit with a local-clocking source flipflop; and connecting a clock output of the local-clocking source flipflop to a clock input of a second D flipflop, wherein the replacing and connecting increases an objective function, the objective function being based on the number of high drive strength cells in a logic cone preceding the second D flipflop.