Invention Grant
- Patent Title: Semiconductor memory devices having adjustable I/O signal line loading that supports reduced power consumption during read and write operations
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Application No.: US18322894Application Date: 2023-05-24
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Publication No.: US12334140B2Publication Date: 2025-06-17
- Inventor: Seung-Jun Lee , Sang-Yun Kim , Jonghyuk Kim , Bok-Yeon Won
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Myers Bigel, P.A.
- Priority: KR10-2022-0122193 20220927
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/4074 ; G11C11/4091 ; G11C11/4093

Abstract:
A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n−1th connection control transistor is configured to electrically short the n−1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.
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Information query