Disclosed herein are related to a memory device. In one aspect, the memory device includes a set of memory cells coupled to a word line, and a tracking cell coupled to a tracking word line and a tracking bit line. In one aspect, the memory device includes a tracking booster circuit coupled to the tracking word line. In one aspect, the tracking booster circuit is configured to boost a first edge of a first pulse applied to the tracking word line. In one aspect, the tracking cell is configured to generate a second pulse at the tracking bit line, in response to the first pulse having the boosted first edge. In one aspect, the memory device includes a word line controller configured to apply a third pulse to the word line, based on the second pulse.