Invention Grant
- Patent Title: Aging monitoring circuit of semiconductor memory device
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Application No.: US18298735Application Date: 2023-04-11
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Publication No.: US12334165B2Publication Date: 2025-06-17
- Inventor: Jae Jin Lee
- Applicant: FIDELIX CO., LTD.
- Applicant Address: KR Seongnam-si
- Assignee: FIDELIX CO., LTD.
- Current Assignee: FIDELIX CO., LTD.
- Current Assignee Address: KR Seongnam-si
- Agency: KILE PARK REED & HOUTTEMAN PLLC
- Priority: KR10-2022-0085353 20220712
- Main IPC: G11C29/50
- IPC: G11C29/50 ; G11C29/02

Abstract:
An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.
Public/Granted literature
- US20240021257A1 AGING MONITORING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2024-01-18
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