Invention Grant
- Patent Title: Multi-height interconnect trenches for resistance and capacitance optimization
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Application No.: US16534063Application Date: 2019-08-07
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Publication No.: US12334392B2Publication Date: 2025-06-17
- Inventor: Kevin Lai Lin , Mauro Kobrinsky , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Haley Guiliano LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528 ; H01L23/522

Abstract:
Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.
Public/Granted literature
- US20210043500A1 MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION Public/Granted day:2021-02-11
Information query
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