A semiconductor memory device comprises: a first conductive and second conductive layers extending in a first direction; and first and second semiconductor column rows aligned in a second direction. The first semiconductor column rows each comprise first semiconductor columns aligned in the first direction and facing the first conductive layer. The second semiconductor column rows each comprise second semiconductor columns aligned in the first direction and facing the second conductive layer. For example, a distance in the first direction between center positions of two of the first semiconductor columns adjacent in the first direction is assumed to be a first adjacent distance. In this case, a pitch in the second direction of the first semiconductor column rows is √3/2 or more times the first adjacent distance. Moreover, a pitch in the second direction of the second semiconductor column rows is less than √3/2 times the first adjacent distance.