Invention Grant
- Patent Title: Clock generation circuit, and semiconductor device and semiconductor system using the clock generation circuit
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Application No.: US18478667Application Date: 2023-09-29
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Publication No.: US12341524B2Publication Date: 2025-06-24
- Inventor: Young Jae An
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si Gyeonggi-do
- Agency: WILLIAM PARK & ASSOCIATES LTD.
- Priority: KR10-2023-0069037 20230530
- Main IPC: H03L7/081
- IPC: H03L7/081 ; H03K5/156 ; H03L7/085 ; H04L7/00
Abstract:
A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.
Public/Granted literature
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