Invention Application
- Patent Title: Test interconnect for bumped semiconductor components and method of fabrication
- Patent Title (中): 凸起半导体元件的测试互连和制造方法
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Application No.: US10832483Application Date: 2004-04-26
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Publication No.: US20040201390A1Publication Date: 2004-10-14
- Inventor: Warren M. Farnworth , Salman Akram
- Main IPC: G01R031/02
- IPC: G01R031/02

Abstract:
An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.
Public/Granted literature
- US07002362B2 Test system for bumped semiconductor components Public/Granted day:2006-02-21
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