Invention Application
- Patent Title: Reducing loadline impedance in a system
- Patent Title (中): 降低系统中的负载线阻抗
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Application No.: US11588682Application Date: 2006-10-27
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Publication No.: US20070074389A1Publication Date: 2007-04-05
- Inventor: Damion Searls , Edward Osburn
- Applicant: Damion Searls , Edward Osburn
- Main IPC: H05K3/30
- IPC: H05K3/30

Abstract:
In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.
Public/Granted literature
- US08659909B2 Method for reducing loadline impedance in a system Public/Granted day:2014-02-25
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