Invention Application
- Patent Title: Enhanced Copper Posts for Wafer Level Chip Scale Packaging
- Patent Title (中): 晶圆级芯片尺寸封装的增强铜柱
-
Application No.: US12899168Application Date: 2010-10-06
-
Publication No.: US20110057313A1Publication Date: 2011-03-10
- Inventor: Kuo-Chin Chang , Han-Ping Pu , Pei-Haw Tsao
- Applicant: Kuo-Chin Chang , Han-Ping Pu , Pei-Haw Tsao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/498
- IPC: H01L23/498

Abstract:
An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.
Public/Granted literature
- US07932601B2 Enhanced copper posts for wafer level chip scale packaging Public/Granted day:2011-04-26
Information query
IPC分类: