Invention Application
- Patent Title: SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US14143700Application Date: 2013-12-30
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Publication No.: US20150155250A1Publication Date: 2015-06-04
- Inventor: Tzu-Chieh Chen , Shih-Chao Chiu , Chia-Cheng Chen
- Applicant: Siliconware Precision Industries Co., Ltd
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd
- Current Assignee: Siliconware Precision Industries Co., Ltd
- Current Assignee Address: TW Taichung
- Priority: TW102143688 20131129
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/522 ; H01L21/768

Abstract:
A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility.
Public/Granted literature
- US09082723B2 Semiconductor package and fabrication method thereof Public/Granted day:2015-07-14
Information query
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