Invention Application
- Patent Title: MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYER
- Patent Title (中): 具有电线束和强化层的微电子封装
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Application No.: US14850500Application Date: 2015-09-10
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Publication No.: US20150380375A1Publication Date: 2015-12-31
- Inventor: Zhijun Zhao , Roseann Alatorre
- Applicant: Invensas Corporation
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/56
Abstract:
Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.
Public/Granted literature
- US09601454B2 Method of forming a component having wire bonds and a stiffening layer Public/Granted day:2017-03-21
Information query
IPC分类:
