An amplifier (100) comprises an input port (102) for receiving an input signal, an envelope port (104) for receiving an envelope signal indicative of an envelope of the input signal. The amplifier has a first transistor (M1) and a second transistor (M2). A first biasing circuit (120) is coupled to the envelope port (104) and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage (140) is coupled to the input port (102) for receiving the input signal, coupled to the first biasing circuit (120) for receiving the first bias voltage, coupled to a gate (g) of the first transistor (M1). A second biasing circuit (130) is coupled between the envelope port (104) and a gate (g 2) of the second transistor (M2), and is arranged to generate a second bias voltage dependent on the envelope signal.