Invention Application
- Patent Title: IMPLEMENTING STRESS IN A BIPOLAR JUNCTION TRANSISTOR
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Application No.: US14874039Application Date: 2015-10-02
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Publication No.: US20170098699A1Publication Date: 2017-04-06
- Inventor: Renata Camillo-Castillo , Qizhi Liu , Vibhor Jain , James W. Adkisson , David L. Harame
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L29/732
- IPC: H01L29/732 ; H01L29/66 ; H01L29/06 ; H01L21/02 ; H01L29/04 ; H01L21/762 ; H01L21/225

Abstract:
Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.
Public/Granted literature
- US09608096B1 Implementing stress in a bipolar junction transistor Public/Granted day:2017-03-28
Information query
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