Invention Application
- Patent Title: ACHIEVING HIGH BANDWIDTH ON ORDERED DIRECT MEMORY ACCESS WRITE STREAM INTO A PROCESSOR CACHE
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Application No.: US15651543Application Date: 2017-07-17
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Publication No.: US20190018775A1Publication Date: 2019-01-17
- Inventor: Ekaterina M. Ambroladze , Timothy C. Bronson , Matthias Klein , Pak-kin Mak , Vesselina K. Papazova , Robert J. Sonnelitter, III , Lahiruka S. Winter
- Applicant: International Business Machines Corporation
- Main IPC: G06F12/0831
- IPC: G06F12/0831 ; G06F13/16

Abstract:
Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.
Public/Granted literature
- US10380020B2 Achieving high bandwidth on ordered direct memory access write stream into a processor cache Public/Granted day:2019-08-13
Information query
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