Invention Application
- Patent Title: PACKAGE SUBSTRATE FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME
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Application No.: US16441591Application Date: 2019-06-14
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Publication No.: US20190295909A1Publication Date: 2019-09-26
- Inventor: Baek KI , Tark-Hyun KO , Kun-Dae YEOM , Yong-Kwan LEE , Keun-Ho JANG , Sang Jin HYUN
- Applicant: Samsung Electronics Co., Ltd.
- Priority: KR10-2016-0117499 20160912
- Main IPC: H01L23/10
- IPC: H01L23/10 ; H01L23/13 ; H01L23/538 ; H01L23/057 ; H01L21/56

Abstract:
A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
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