Invention Application
- Patent Title: PHASE LOCK LOOP (PLL) WITH OPERATING PARAMETER CALIBRATION CIRCUIT AND METHOD
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Application No.: US17519122Application Date: 2021-11-04
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Publication No.: US20220200607A1Publication Date: 2022-06-23
- Inventor: Ankit GUPTA
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Main IPC: H03L7/099
- IPC: H03L7/099 ; H03L7/089 ; H03L7/093

Abstract:
A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.
Public/Granted literature
- US11418204B2 Phase lock loop (PLL) with operating parameter calibration circuit and method Public/Granted day:2022-08-16
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