Invention Application
- Patent Title: SPLIT-GATE TRENCH MOS TRANSISTOR WITH SELF-ALIGNMENT OF GATE AND BODY REGIONS
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Application No.: US17553477Application Date: 2021-12-16
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Publication No.: US20220208995A1Publication Date: 2022-06-30
- Inventor: Davide Giuseppe PATTI
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Priority: IT102020000032771 20201230
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L29/40 ; H01L21/225 ; H01L21/265 ; H01L21/765
Abstract:
A process is proposed for manufacturing an integrated device having at least one MOS transistor integrated on a die of semiconductor material. The process includes forming one or more gate trenches with corresponding field plates and gate regions. A body region is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface of the die. Moreover, a corresponding integrated device and a system comprising this integrated device are proposed.
Information query
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