Semiconductor devices may include a gate stack including electrode layers stacked alternately with insulating layers and channel structures in the electrode layers and the insulating layers; a cell region insulating layer and an upper support layer on the gate stack; and a separation region in the gate stack and the cell region insulating layer. The separation regions may include a first separation region in the upper support layer and a second separation region below the upper support layer. The first separation region may include a first region in the upper support layer, a second region in the cell region insulating layer, and a third region in the gate electrode layers. The first separation region may further include has a first bend portion in the second region and a second bend portion that may be higher than the first bend portion and uppermost surfaces of the channel structures.