Invention Publication
- Patent Title: METHOD FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION
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Application No.: US18151527Application Date: 2023-01-09
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Publication No.: US20230152713A1Publication Date: 2023-05-18
- Inventor: Cheng-Kuan WU , Po-Chung CHENG , Li-Jui CHEN , Chih-Tsung SHIH
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- The original application number of the division: US16019732 2018.06.27
- Main IPC: G03F7/20
- IPC: G03F7/20

Abstract:
A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer over a wafer stage. The method also includes supplying an initial voltage to a plurality of electrodes of the wafer stage based on a topology of the semiconductor wafer, wherein the electrodes of the wafer stage are electrically isolated from each other. The method further includes measuring an adjusted topology of the semiconductor wafer after the initial voltage is supplied. In addition, the method includes supplying different first adjusted voltages to the electrodes of the wafer stage according to the adjusted topology of the semiconductor wafer.
Public/Granted literature
- US12025918B2 Method for lithography in semiconductor fabrication Public/Granted day:2024-07-02
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