Invention Publication
- Patent Title: SENSE AMPLIFIER CIRCUIT AND DATA READ METHOD
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Application No.: US18149675Application Date: 2023-01-04
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Publication No.: US20230162762A1Publication Date: 2023-05-25
- Inventor: Guifen YANG , SUNGSOO CHI
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Priority: CN 2111405425.7 2021.11.24
- Main IPC: G11C7/06
- IPC: G11C7/06 ; G11C7/12 ; G11C7/10

Abstract:
Embodiments relate to a sense amplifier circuit and a data read method. The sense amplifier circuit includes: a first P-type transistor connected to a first signal terminal; a second P-type transistor connected to a second signal terminal; a first N-type transistor connected to a third signal terminal; a second N-type transistor connected to a fourth signal terminal; a first offset cancellation subcircuit configured to connect a first read bit line to a second complementary read bit line in response to a first offset cancellation signal; a second offset cancellation subcircuit configured to connect a first complementary read bit line to a second read bit line in response to a second offset cancellation signal; a first write-back subcircuit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal; and a second write-back subcircuit.
Public/Granted literature
- US12112824B2 Sense amplifier circuit and data read method Public/Granted day:2024-10-08
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