Invention Publication
- Patent Title: MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
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Application No.: US17817405Application Date: 2022-08-04
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Publication No.: US20230171938A1Publication Date: 2023-06-01
- Inventor: Deyuan XIAO , Yong Yu , Guangsu Shao
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. , BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
- Applicant Address: CN Hefei City
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.,BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.,BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
- Current Assignee Address: CN Hefei City
- Priority: CN 2111440472.5 2021.11.30
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/78

Abstract:
The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array on the substrate, where the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially, and along a second direction, a cross-sectional area of the second segment is smaller than those of the first segment and the third segment; forming a gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a gate dielectric layer on the gate oxide layer, where the gate dielectric layer is shorter than the gate oxide layer, and is close to the third segment.
Information query
IPC分类: