Invention Publication
- Patent Title: METHOD AND SYSTEM FOR TRACING ERROR OF LOGIC SYSTEM DESIGN
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Application No.: US17559032Application Date: 2021-12-22
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Publication No.: US20230176941A1Publication Date: 2023-06-08
- Inventor: Yang-Trung LIN
- Applicant: XEPIC CORPORATION LIMITED
- Applicant Address: CN Nanjing
- Assignee: XEPIC CORPORATION LIMITED
- Current Assignee: XEPIC CORPORATION LIMITED
- Current Assignee Address: CN Nanjing
- Priority: CN 2111491365.5 2021.12.08
- Main IPC: G06F11/16
- IPC: G06F11/16 ; G06F11/07 ; G06N20/00

Abstract:
A method for tracing an error of a logic system design includes obtaining an assertion failure of a combinational cone of the logic system design, the combinational cone including a plurality of sub-cones; and obtaining machine learning models of the sub-cones. Each sub-cone represents a sub-circuitry of the logic system design and has one or more input signals and an output signal. The assertion failure indicates an actual signal value of the combinational cone at a current clock cycle being different from an expected output value at the current clock cycle. The method also includes: performing backtracing on the sub-cones according to the assertion failure, the machine learning models of the sub-cones, and dynamic backtracing sensitivities corresponding to the sub-cones, to obtain a backtracing result; and outputting one or more target sub-cones as candidate root causes of the assertion failure according to the backtracing result.
Public/Granted literature
- US11841761B2 Method and system for tracing error of logic system design Public/Granted day:2023-12-12
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