Disclosed is a method of designing and fabricating a semiconductor chip including a fuse cell. The method may include preparing a semiconductor chip layout, the semiconductor chip layout including a main chip layout and a scribe lane layout enclosing the main chip layout; disposing a fuse layout in the scribe lane layout; setting the main chip layout as a first data preparation region; setting the scribe lane layout and the fuse layout as a second data preparation region; obtaining a first resulting structure and a second resulting structure, respectively, by performing a data preparation process on the first and second data preparation regions; merging the first and second resulting structures to generate mask data; manufacturing a photomask, based on the mask data; and forming semiconductor chips on a wafer using the photomask.