A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.