Invention Application
- Patent Title: SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESET, AND DATA CORRUPTION MODES FOR SECURE APPLICATIONS
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Application No.: US17853026Application Date: 2022-06-29
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Publication No.: US20230018420A1Publication Date: 2023-01-19
- Inventor: Praveen Kumar VERMA , Promod KUMAR , Harsh RAWAT
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Main IPC: G11C8/20
- IPC: G11C8/20 ; G11C11/418

Abstract:
A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.
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