Invention Publication
- Patent Title: TESTING METHOD FOR PACKAGED CHIP, TESTING SYSTEM FOR PACKAGED CHIP, COMPUTER DEVICE AND STORAGE MEDIUM
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Application No.: US17615566Application Date: 2021-05-17
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Publication No.: US20230187005A1Publication Date: 2023-06-15
- Inventor: Cheng-Jer YANG
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei City, Anhui
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei City, Anhui
- Priority: CN 2010689689.9 2020.07.17
- International Application: PCT/CN2021/094113 2021.05.17
- Date entered country: 2021-11-30
- Main IPC: G11C29/10
- IPC: G11C29/10

Abstract:
The present application relates to a testing method for a packaged chip, a testing system for a packaged chip, a computer device and a storage medium. The method includes following steps: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time, and subsequent testing will be performed continuously. Moreover, since the products satisfying the requirements can be screened out in the bum-in test process, compared with the prior art, the test cost is reduced, and the test efficiency is improved.
Public/Granted literature
- US11862269B2 Testing method for packaged chip, testing system for packaged chip, computer device and storage medium Public/Granted day:2024-01-02
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